Time-to-digital conversion circuitry is circuitry for measuring an amount of time delay between two or more digital signals, a time difference between two different edges of one digital signal, and so on by using digital values. The time-to-digital conversion circuitry is utilized in various fields of science and technology, such as the fields of communication, the fields of nuclear power, and the fields of electronic circuitry. Specifically, the time-to-digital conversion circuitry is used incorporated into LiDAR, which is an optical system for measuring the time of flight of a photon that is very weak light, phase-locked loops, which are integrated circuitry, analog-to-digital converting circuitry, and so on.
NPL 1 discloses time-to-digital conversion circuitry having high linearity. The configuration of this time-to-digital conversion circuitry is illustrated in FIG. 1.
As illustrated in FIG. 1, a TDC (Time-to-Digital Converter) 100 comprises a DLL (Delay-Locked Loop) 101, a ripple counter 102, and phase sampling circuitry 103, 104.
A clock CLK1 is input to the DLL 101 and the ripple counter 102. The DLL 101 includes a VCDL (Voltage Controlled Delay Line) 1011. The phase sampling circuitry 103 samples a plurality of phase signals from the VCDL 1011 in synchronization with a start signal START output from a system 105 to be observed. The phase sampling circuitry 104 samples the plurality of phase signals from the VCDL 1011 in synchronization with a stop signal STOP output from the system 105.
The ripple counter 102 starts counting edges of the clock CLK1 in synchronization with the start signal START and stops the counting in synchronization with the stop signal STOP.
The ripple counter 102, the phase sampling circuitry 103, and the phase sampling circuitry 104 output a digital count value COUT, a sampled value PSTART, and a sampled value PSTOP, respectively. An amount-of-delay measurement value TDC_OUT between the start signal START and the stop signal STOP is calculated according to equation (1) below, based on the count value COUT, the sampled value PSTART, and the sampled value PSTOP.TDC_OUT=COUT·8+(PSTOP−PSTART)  (1)where one cycle of the phase signals output from the VCDL 1011 is assumed to be equal to one cycle of the clock CLK1. Also, 8-bit phase signals input to the phase sampling circuitry 103, 104 are assumed to be signals obtained by delaying one cycle of the clock CLK1 into eight different phases.
Meanwhile, a Sliding Scale Technique is stated in NPL 1 as a method for improving linearity of an AD conversion circuitry. In this method, a random signal is added to an input signal of the AD conversion circuitry, the signal is subjected to AD conversion, and an amount corresponding to the random signal is subtracted from the result of the AD conversion. This operation can alleviate nonlinearity of the AD conversion circuitry. Use of a Cyclic Sliding Scale Technique (CSST) in which this idea is applied to a TDC can improve the linearity of the TDC with a simple configuration.
Now, a method for realizing the CSST will be briefly described.
Since the clock CLK1 for the TDC 100 is generally generated from crystal oscillator circuitry, the cycle of the clock CLK1 is accurate, and the count value COUT is also accurate, that is, the linearity of the count value COUT is high. Meanwhile, since delay characteristics of delay elements that constitute the VCDL 1011 vary, the 8-bit phase signals cannot equally divide one cycle of the clock CLK1. Variations in the delay characteristics influence phase-signal sampling performed by phase sampling circuitry 103, 104 and consequently become a major factor that causes nonlinearity in an output of the TDC 100, that is, the amount-of-delay measurement value TDC_OUT.
The TDC 100 uses the CSST to alleviate the influences of the nonlinearity. Thus, in the TDC 100, the phase sampling circuitry 103 is provided for the start signal START, and the phase sampling circuitry 104 is also provided for the stop signal STOP. Also, the TDC 100 makes the 8-bit phase signals of the VCDL 1011 asynchronous with the start signal START and the stop signal STOP. This can improve the linearity of the TDC 100. In order to realize the above-described asynchronization, the system 105 is operated with a clock CLK2, which is asynchronous with the clock CLK1.
Unlike the TDC 100 in FIG. 1, a TDC (FIG. 8(a) and FIG. 8(b)) disclosed in NPL 2 uses a PLL (Phase-Locked Loop) and a VCO (Voltage Controlled Oscillator) instead of a DLL and a VCDL, respectively. The configuration of this TDC is illustrated in FIG. 2.
A TDC 200 illustrated in FIG. 2 comprises a ripple counter 102, phase sampling circuitry 103, 104, and a PLL 201.
The PLL 201 includes a VCO 2011. The phase sampling circuitry 103 samples a plurality of phase signals from the VCO 2011 in synchronization with a start signal START from a system 105. The phase sampling circuitry 104 samples the plurality of phase signals from the VCO 2011 in synchronization with a stop signal STOP from the system 105.
The ripple counter 102 starts counting, as an input clock, a particular phase signal output from the VCO 2011, in synchronization with the start signal START, and stops the counting in synchronization with the stop signal STOP.
The ripple counter 102, the phase sampling circuitry 103, and the phase sampling circuitry 104 output a digital count value COUT, a sampled value PSTART, and a sampled value PSTOP, respectively. An amount-of-delay measurement value TDC_OUT between the start signal START and the stop signal STOP is calculated according to equation (1) noted above, based on the count value COUT, the sampled value PSTART, and the sampled value PSTOP.
In this case, it is assumed that 4-bit phase signals input to the phase sampling circuitry 103, 104 are signals obtained by dividing one cycle of phase signals output from the VCO 2011 into eight, phases.
Thus, the TDC 200 illustrated in FIG. 2 also has a configuration to which CSST is applied, as in the TDC 100 in FIG. 1. Accordingly, it is possible to improve nonlinearity of the TDC 200 which is caused by variations in the delay characteristics of delay elements that constitute the VCO 2011.
In a TDC (FIG. 5.26 and FIG. 5.27) disclosed in NPL 3 a PLL 201 is not included, and oscillation operation of a VCO is turned ON/OFF in accordance with a start signal START and a stop signal STOP, unlike the TDC 200 in FIG. 2. The configuration of this TDC is illustrated in FIG. 3.
As illustrated in FIG. 3, a TDC 300 comprises a ripple counter 301, a VCO 302, phase sampling circuitry 303, reset circuitry 304 (in the figure, RSTGEN), and an SR latch 305.
The VCO 302 has a reset terminal RST and an enable terminal EN. A reset signal supplied from the reset circuitry 304 in order to set an internal state of the VCO 302 to a reset state is input to the reset terminal RST. An enable signal for controlling ON/OFF of the oscillation operation is input to the enable terminal EN.
The ripple counter 301 counts, as an input clock, a particular phase signal output from the VCO 302. The phase sampling circuitry 303 samples 4-bit phase signals of the VCO 302 in synchronization with the stop signal STOP.
The reset circuitry 304 resets the ripple counter 301 and the VCO 302 before time measurement upon the start signal START. The SR latch 305 controls ON/OFF of the VCO 302.
In this case, the VCO 302 performs oscillation when the potential level of the enable terminal EN is high and stops the oscillation when the logic level of the enable terminal EN is low. Also, an output signal of the SR latch 305 goes high in synchronization with the start signal START and goes low in synchronization with the stop signal STOP. A system 105 operates with a clock CLK1, as in the TDC 300.
In a typical system, a start signal START or a stop signal STOP is synchronous with an operation clock of a TDC. Thus, the TDC 300 illustrated in FIG. 3 uses the clock CLK1 that is common to the system 105.
In this case, since the TDC 300 does not comprise a PLL, the VCO 302 oscillates in a free-running manner. Accordingly, the oscillation frequency of the VCO 302 is uncorrelated with the frequency of the clock CLK1. Also, after the VCO 302 is reset to a certain predetermined state in response to a reset, signal from the reset circuitry 304 before time measurement upon the start signal START, the VCO 302 starts oscillation in synchronization with the start signal START and stops the oscillation in synchronization with the stop signal STOP. That is, immediately before the VCO 302 starts oscillation in synchronization with the start signal START, the phase signals of the VCO 302 are always fixed to the aforementioned reset state.
Accordingly, the 4-bit phase signals output from the VCO 302 and the start signal START are thought to be synchronous with each other. Thus, the TDC 300 cannot use CSST, making it difficult to enhance the linearity.